| CONFERENCE PROGRAMME |
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| DESDes09 |
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| 6th October 2009, Tuesday |
Opening session
Chairman: Prof Marian Adamski
08:30 - 08:45
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Invited Session. S. Baranov. Israel.
Chairman: Prof Marian Adamski
08:45 - 09:30
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1. |
ASMs in High Level Synthesis of EDA tool Abelite |
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Samary Baranov |
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08:45-09:30 |
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Session 1a. Formal methods in Digital Design I.
Chairman: Dr Monica Leba
09:45 - 10:45
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1. |
Design of Reconfigurable Logic Controllers
from Petri Net-based specifications
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Marian Adamski, Marek Węgrzyn |
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09:45-10:05 |
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2. |
A High Level Modeling Approach for
Reconfigurable System Architecting
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L. Dorie, Olivier Pasquier, S. Le Nours, JF. Diouris |
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10:05-10:25 |
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3. |
Algebra-Logical Diagnosis and Repair
Method for SoC Memory |
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Vladimir Hahanov, Eugenia Litvinova, Olesya Guz, Tiecoura Yves |
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10:25-10:45 |
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Session 1b. Design and verification.
Chairman: Prof Samary Baranov
09:45 - 10:45
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1. |
Dynamic partial reconfiguration of CPU-s
for Programmable Logic Controllers executing control programs developed
in the Ladder Diagram language
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Miroslaw Chmiel, Jan Mocha, Dariusz Kania, Edward Hrynkiewicz |
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09:45-10:05 |
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2. |
Smoothing and simpli fication algorithm
for Computer Aided Manufacturing paths with complex curves
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Javier Lamas, Alberto Ramil, Armando Yañez |
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10:05-10:25 |
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3. |
A Comparative Analysis of two Verification
Techniques for DEDS: Model Checking versus Model-based Testing
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Rodrigo Pastl Pontes, Marcelo Essado, Paulo Claudino Veras, Ana Maria Ambrosio, Emilia Villani |
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10:25-10:45 |
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Session 2. Petri Nets and Industrial Control.
Chairman: Prof Edward Hrynkiewicz
11:15 - 13:15
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1. |
Representation of the State of Timed-Place
Petri Nets Using Stretching |
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Aydin Aybar, Altug Iftar |
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11:15-11:35 |
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2. |
Ladder diagram implementation of Control
Interpreted Petri Nets: a state equation approach
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Marcos Moreira, Daniel Botelho, Joao Basilio |
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11:35-11:55 |
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3. |
Digital System Design Process Automation
Using Place/Transition Petri Nets
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Norian Marranghello, Alexandre Silva, Aledir Pereira |
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11:55-12:15 |
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4. |
Spring Orthosis with Inclined Indoor
Rowing Exercise for Paraplegics
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Z. Hussain, Mohammad Osman Tokhi, Rozita Jailani |
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12:15-12:35 |
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5. |
Enhanced Interpreted Petri Nets for
Industrial Processes |
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Eid Alhajri, J.A. Rossiter |
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12:35-12:55 |
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6. |
Firmware Optimization for Embedded Logic Control |
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Václav Dvořák, Petr Mikušek |
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12:55-13:15 |
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Session 3. Digital Communication Systems.
Chairman: Prof Urlich Jumar
15:00 - 16:20
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1. |
Communication with autonomous mobile vehicles |
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Jiri Bayer, Jan Bilek, Petr Heinrich, Jan Mareček, Jiří Bittner, Miroslav Muller, Ondřej Zeman, Jiří Zemánek, Ondřej Šantin |
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15:00-15:20 |
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2. |
Bit accurate timing analysis on a frame
based CAN model |
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Marcus Müller, Johannes Klockner, Wolfgang Fengler |
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15:20-15:40 |
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3. |
Certificate based security at device level
of automation system |
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Olli Post, Jari Seppälä, Hannu Koivisto |
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15:40-16:00 |
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4. |
Performance Analysis of Reconfigurable
Clusters to Design Good Error Correcting Codes in Communications
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Juan A. Gomez-Pulido, Miguel A. Vega-Rodríguez, Juan M. Sánchez-Pérez |
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16:00-16:20 |
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TC3.1 Meeting
16:30 - 17:30
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| 7th October 2009, Wednesday |
Invited Session 2. Low Power Techniques for embedded SoC. Medical applications. Mr. Alberto Sánchez. Analog Devices.
Presenter(s): Mr Joan Vila-Francés
08:30 - 09:30
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Poster Session
09:30 - 11:00
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1. |
Analysis of Resource Utilization in
Compositional Microprogram Control Unit with Elementary Operational
Linear Chains |
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Małgorzata Kołopieńczyk, Larysa Titarenko |
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2. |
Partitioning of Mealy Finite State Machines |
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Arkadiusz Bukowiec, Luis Gomes |
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3. |
Modeling of production processes using UML
and Petri nets. |
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Agnieszka Lasota, Andrei Karatkevich |
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4. |
Embedded WWW Server in Wireless Sensor Networks |
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Iwona Grobelna, Michał Grobelny, Agnieszka Węgrzyn, Marek Węgrzyn |
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5. |
Apnea Detection Using Cardiac Rhythm and
its Hardware Implementation |
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Juan Guerrero Martínez, Alfredo Rosado-Muňoz, Manuel Bataller Mompeán, Francisco Megía Marco, C. Molinos-Solsona |
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6. |
Remote, web-based laboratory for
Programmable Logic Devices |
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Przemysław Iskra, Alfredo Rosado-Muňoz |
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Session 4. Digital Systems.
Chairman: Prof Vladimir Hahanov
09:45 - 10:45
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1. |
Shared Memory Networks On Chip Architecture |
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Piotr Dziurzanski, Lukasz Tyczynski, Tomasz Maka |
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09:45-10:05 |
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2. |
RecDEVS: A Comprehensive Model of
Computation for Dynamically Reconfigurable Hardware Systems
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Felix Madlener, Alexander Biedermann, Sorin A. Huss |
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10:05-10:25 |
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3. |
A Novel Approach to Evaluate Passive
Elastic-viscosity and Mass for Lower Limb
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Z. Hussain, Mohammad Osman Tokhi, Babul Salam KSM Kader Ibrahim, Rozita Jailani |
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10:25-10:45 |
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Session 5. Formal methods in Digital Design II.
Chairman: Prof Václav Dvořák
11:15 - 13:15
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1. |
Minimizing the number of PAL macrocells for Moore FSM |
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Alexander A. Barkalov, Larysa Titarenko, Sławomir Chmielewski |
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11:15-11:35 |
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2. |
A System Level Design Flow for Embedded
Systems based on Model of Computation Mappings
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Hans Gregor Molter, Felix Madlener, Sorin A. Huss |
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11:35-11:55 |
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3. |
Supervisory control in structured dynamic
discrete-event systems |
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Alexander Ambartsumyan |
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11:55-12:15 |
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4. |
Straight encoding method of supervisor
implementation for structured discrete dynamic event system
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Alexander Ambartsumyan, Eugene Tomilin, Sergey Branishtov |
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12:15-12:35 |
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5. |
Algebra-Logical Fault Diagnosis Method For
SOC Functional Blocks |
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Vladimir Hahanov, Svetlana Chumachenko, Wajeb Gharibi, Ngene Christopher Umerah |
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12:35-12:55 |
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6. |
Analysis of Concurrent Discrete Systems by
Means of Reduced Reachability Graphs
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Andrei Karatkevich |
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12:55-13:15 |
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| 8th October 2009, Thursday |
Invited Session 3. Brazil-IP - an approach to digital systems synthesis. Norian Marranghello. UNESP. Brasil.
Presenter(s): Dr Alfredo Rosado-Muňoz
08:30 - 09:30
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Session 6. Artificial Intelligence and Adaptive Systems.
Chairman: Dr Marek Węgrzyn
09:45 - 10:45
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1. |
Adaptive algorithms robust to impulsive
noise with low computational cost using Order Statistic
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Emilio Soria Olivas, Jose D. Martin-Guerrero, Antonio J. Serrano, Rafael Magdalena, Marcelino Martınez, Juan Gómez Sanchis |
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09:45-10:05 |
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2. |
Digital Controller Design Based on Logic
Neural Networks |
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Emil Pop, Monica Leba |
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10:05-10:25 |
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3. |
Synthesis of Microprogram Control Unit
with Control Microinstructions
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Alexander A. Barkalov, Larysa Titarenko, Jacek Bieganowski |
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10:25-10:45 |
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Session 7. Logic Synthesis
Chairman: Prof Alexander A. Barkalov
11:15 - 13:15
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1. |
Frequency Multiplication with Utilisation
of Walsh Functions |
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Edward Hrynkiewicz |
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11:15-11:35 |
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2. |
A notion of r-admissibility and its
application in logic synthesis
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Grzegorz Borowik, Tadeusz Łuba, Paweł Tomaszewicz |
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11:35-11:55 |
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3. |
Multi-Level Implementation of Asynchronous
Logic Using Two-Level Nodes |
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Igor Lemberski, Petr Fiser |
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11:55-12:15 |
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4. |
Reconfiguration Strategy for FPGA
Dependability Characteristics Improvement based on Stochastic Petri Net
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Martin Kohlík, Hana Kubátová |
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12:15-12:35 |
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5. |
Statechart Diagrams Implementation in FPGA
Structures in Embedded Memory Blocks
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Grzegorz Łabiak, Grzegorz Borowik |
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12:35-12:55 |
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6. |
Hardware Implementation of a Robust
Adaptive Filter: Two Approaches based in High-Level Synthesis Design
Tool |
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Manuel Bataller Mompeán, Alfredo Rosado-Muňoz, Emilio Soria Olivas, Juan Guerrero Martínez, Joan Vila-Francés |
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12:55-13:15 |
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